The present invention relates to fabrication of leads on microelectronic elements such as semiconductor wafers and chips and to microelectronic elements having such leads thereon.
Microelectronic elements such as semiconductor chips typically are formed as solid elements with contacts on a front face. For example, semiconductor chips are typically formed by processing a large, flat disk-like wafer to form the internal electronic components of numerous semiconductor chips, the elements of each of such chip being disposed within a small, typically rectangular region of the wafer. The pads in each region are connected to the internal electronic components in that region. Typically, a passivation layer is applied on the front surface of the layer and provided with openings aligned with the pads. The passivation layer protects the internal components of the layer from contamination. After the wafer has been processed, the wafer is cut so as to separate the regions from one another to yield individual semiconductor chips.
Individual semiconductor chips can be mounted directly to a circuit board or other substrate by solder-bonding the contact pads of the chip directly to the circuit board, a process commonly referred to as “flip-chip” interconnection. However, such connections suffer from significant drawbacks including difficulties in testing chips before they are assembled to the circuit board and failure of the solder bonds due to stresses caused by thermal expansion and contraction of the components during manufacture and use. To avoid these difficulties, semiconductor chips have been mounted to circuit boards heretofore by wire-bonding. In wire-bonding, the chip is mounted face-up, with the contact bearing front face of the chip facing upwardly, away from the circuit board. Small wires are connected between individual contacts on the chip and the corresponding connections on the circuit board. As described, for example, in Matunami, U.S. Pat. No. 3,952,404 and Luro, U.S. Pat. No. 3,825,353, it has been proposed to provide leads on chips connected to the contact pads of the chips. The leads may be subsequently bonded to a circuit board or other substrate.
Other approaches to handling and mounting semiconductor chips include mounting the chips in packages having exposed terminals connected to the chip contacts and bonding the terminals of the packages to the circuit board. Numerous designs for chip packages have been proposed. Many of these involve packages structures which are considerably larger than the chips themselves. Moreover, some chip packages provide do not provide electrical connections with adequate reliability. As disclosed in the preferred embodiments of commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,518,964, the disclosures of which are hereby incorporated by reference herein, as well as other commonly assigned patents, a package semiconductor chip can be provided with terminals overlying a face of the chip and electrically connected to the contacts of the chip. Most commonly, the terminals are disposed on a supporting dielectric layer and a compliant layer such as a gel or elastomer may be disposed between the terminals and the chips as to mechanically de-couple the terminals from the chip and allow movement of the terminals with respect to the chip. Certain embodiments taught in these patents use flexible leads interconnecting the terminals and the chip. Although various fabrication methods may be employed to produce these assemblies, such assemblies most commonly are formed by fabricating the dielectric with the leads and terminals thereon and attaching the dielectric to the chips, either before or after severing the chips from the wafer. As described in co-pending, commonly assigned U.S. patent application No. 09/217,675, filed May 24, 1999, the disclosure of which is incorporated by reference herein, leads formed on the surface of a chip or wafer can be reliably interconnected with another element such as a circuit panel bearing leads.
The approaches disclosed in these commonly assigned patents and applications provide useful solutions to the problems of handling and mounting microelectronic elements such as semiconductor chips. Nonetheless, further development and additional solutions would be desirable.